1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device capable of placing large stress on a specific transistor in a burn-in test mode.
2. Description of the Background Art
FIG. 19 is a circuit diagram showing configurations of a word line driver and its peripheral in a conventional dynamic random access memory (DRAM). Referring to FIG. 19, the word line driver 1 for driving a word line WL includes a P channel MOS transistor 2 and N channel MOS transistors 3 and 4. A memory cell 5 is connected to word line WL and a bit line BL.
When word line WL is selected, as shown in FIG. 20A, a sub-decode signal xcfx86 attains an H (logical high) level (of a boosted potential Vpp greater than a power supply potential), a sub-decode signal Zxcfx86 attains an L (logical low) level (of a ground potential), and the potential of a main word line ZMWL (i.e., a main word line select signal) attains an L level. As a result, transistor 2 turns on and transistors 3 and 4 turn off, so that the potential of word line WL becomes boosted potential Vpp. Throughout the specification and drawings, a reference character xe2x80x9cZxe2x80x9d prefixed to any signal indicates that the relevant signal is low active.
When word line WL is not selected, as shown in FIG. 20B, although sub-decode signal xcfx86 attains an H level and sub-decode signal Zxcfx86 attains an L level, the potential of main word line ZMWL (main word line select signal) is maintained at the H level (of boosted potential Vpp greater than the power supply potential). As a result, transistors 3 and 4 turn on, and transistor 2 basically turns off, while a small leakage current Ilk flows in transistor 2. If this leakage current Ilk is large, the potential of word line WL will become greater than the ground potential, which is likely to damage data of memory cell 5. Any DRAM having P channel MOS transistor 2 with such a large leakage current Ilk should be eliminated from end products.
FIG. 21 is a circuit diagram showing configurations of a sense amplifier and its peripheral in a conventional DRAM. Referring to FIG. 21, the sense amplifier 6 is connected to a bit line pair BL, ZBL through a bit line isolating gate 7. Sense amplifier 6 is also connected to an input/output line pair I/O, ZI/O through a column select gate 8. Column select gate 8 is formed of N channel MOS transistors 81 and 82. Connected to input/output line pair I/O, ZI/O is a write driver 9 that responds to a write driver enable signal ZWDE and transmits write data WD to bit line pair BL, ZBL. An equalizing circuit 10 is also connected to input/output line pair I/O, ZI/O, which responds to an equalizing signal IOEQ and equalizes the potentials of input/output lines I/O and ZI/O.
When data is being written, as shown in FIG. 22, a bit line isolating signal BLI attains an H level, a bit line isolating gate 7 is turned on, and bit line pair BL, ZBL is connected to sense amplifier 6. Thereafter, when sense amplifier 6 is activated, data of an L level is read out in this example, so that bit line pair BL attains a potential of an L level, and bit line ZBL attains a potential of an H level. Thereafter, when write driver enable signal ZWDE attains an L level, write driver 9 responds to write data WD of an H level in this example, and drives the potential of input/output line I/O to an H level and the potential of input/output line ZI/O to an L level. Thereafter, when a column select signal CSL attains an H level, column select gate 8 is turned on, and the potentials of input/output line pair I/O, ZI/O are transmitted to bit line pair BL, ZBL. In this case, although the potentials of bit line pair BL, ZBL are opposite to the potentials of input/output line pair I/O, ZI/O, write driver 9 is able to reverse the potentials of bit line pair BL, ZBL, since it has driving capability greater than that of sense amplifier 6. Specifically, the potential of bit line BL is turned to an H level, and the potential of bit line ZBL is turned to an L level.
If transistors 81 and 82 of column select gate 8 each have a large ON resistance, however, the potentials of input/output line pair I/O, ZI/O will not be transmitted sufficiently to bit line pair BL, ZBL while column select signal CSL is at an H Level. In this case, write driver 9 will fail to reverse the potentials of bit line pair BL, ZBL, causing an error in data writing. Therefore, any DRAM having transistors 81, 82 with such large ON resistances should be eliminated from end products.
A conceivable way of finding the former defective transistor 2 will be, in a burn-in test, to raise the potential of sub-decode signal xcfx86 greater than boosted potential Vpp and repeat selection/non-selection of word line WL to accelerate the stress being imposed on transistor 2, thereby increasing leakage current Ilk. In this case, however, an enormous amount of consumption current will flow. Thus, due to the constraint of the burn-in tester, the frequency of repetition of the selection/non-selection of the word line is limited to some extent.
A possible way to find the latter defective transistors 81, 82 will be, in a burn-in test, to repeat writing of data of an H level and data of an L level to accelerate the stress being imposed on transistors 81, 82, thereby increasing the ON resistances thereof. However, a huge amount of consumption current will flow again in this case. Thus, due to the constraint of the burn-in tester, the data writing cannot be repeated so frequently.
An object of the present invention is to provide a semiconductor memory device capable of imposing large stress on a specific transistor.
According to an aspect of the present invention, the semiconductor memory device includes a word line, a word line driver, and a word line select circuit. The word line driver drives the word line. The word line select circuit generates a word line select signal for selecting the word line. The word line driver includes a first transistor and a second transistor. The first transistor has one conductive electrode receiving a boosted potential greater than a power supply potential, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The second transistor has one conductive electrode grounded, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The semiconductor memory device further includes a turn-on circuit which causes the first transistor to turn on in response to a test signal.
In this semiconductor memory device, the first transistor is turned on in response to the test signal even when the word line is non-selected, and a leakage current flows in the first transistor. As a result, it is possible to impose large stress on the first transistor.
According to another aspect of the present invention, the semiconductor memory device includes a plurality of blocks, each of which is selected in response to a corresponding block select signal. Each block includes a word line, a word line driver, and a word line select circuit. The word line driver drives the word line. The word line select circuit generates a word line select signal for selecting the word line. The word line driver includes a first transistor and a second transistor. The first transistor has one conductive electrode receiving a boosted potential greater than a power supply potential, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The second transistor has one conductive electrode grounded, another conductive electrode connected to the word line, and a control electrode receiving the word line select signal. The semiconductor memory device further includes a turn-on circuit. The turn-on circuit causes the first transistor in selected one of the blocks to turn on in response to a test signal.
In this semiconductor memory device, the first transistor is turned on in response to the test signal even if the word line is not selected, so that a leakage current flows in the first transistor. As a result, it is possible to impose large stress on the first transistor. In addition, the leakage current flows only in the selected block, not in a non-selected block. This reduces current consumption during the test.
Preferably, the turn-on circuit responds to the test signal and drives the word line select signal to a potential lower than the boosted potential.
Still preferably, the turn-on circuit provides a power supply of the word line select circuit with a potential lower than the boosted potential when the test signal is in an active state, and provides the same with the boosted potential when the test signal is in an inactive state. The word line select circuit drives the word line select signal to a ground potential when the word line is selected, and drives the same to the potential provided to the power supply of the word line select circuit when the word line is not selected.
According to a further aspect of the present invention, the semiconductor memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, an input/output line pair, a plurality of column select gates, and a turn-on circuit. The sense amplifiers are provided for the bit line pairs, and each sense amplifier is connected to the corresponding bit line pair. The column select gates are provided for the bit line pairs, and each column select gate is connected between the corresponding bit line pair and the input/output line pair. The turn-on circuit causes the column select gates to turn on in response to a test signal.
In this semiconductor memory device, the plurality of column select gates are turned on in response to the test signal, and the plurality of bit line pairs are connected to the input/output line pair. If data of an H level and data of an L level are written repeatedly at this time, large stress can be imposed on the column select gates.
Preferably, the semiconductor memory device further includes a plurality of bit line isolating gates and a turn-off circuit. The bit line isolating gates are provided for the bit line pairs. Each bit line isolating gate is connected between the corresponding bit line pair and the corresponding sense amplifier. The turn-off circuit causes the bit line isolating gates to turn off in response to the test signal.
When the plurality of bit line isolating gates are turned off in response to the test signal, the plurality of bit line pairs are disconnected from the corresponding sense amplifiers. As a result, it is unnecessary to charge/discharge the bit line pairs while repeating the data writing, and thus, the current consumption can be reduced.
According to yet another aspect of the present invention, the semiconductor memory device includes an input/output line pair and a plurality of blocks. Each block is selected in response to a corresponding block select signal. Each block includes a plurality of bit line pairs, a plurality of sense amplifiers, and a plurality of column select gates. The sense amplifiers are provided for the bit line pairs. Each sense amplifier is connected to the corresponding bit line pair. The column select gates are provided for the bit line pairs. Each column select gate is connected between the corresponding bit line pair and the input/output line pair. The semiconductor memory device further includes a turn-on circuit. The turn-on circuit causes the column select gates in selected one of the blocks to turn on in response to a test signal.
In this semiconductor memory device, the plurality of column select gates are turned on in response to the test signal, and the plurality of bit line pairs are connected to the input/output line pair. If data of an H level and data of an L level are repeatedly written at this time, large stress can be imposed on the column select gates. In addition, the plurality of bit line pairs only in the selected block are connected to the input/output line pair, while the bit line pairs in a non-selected block are not connected thereto. This reduces the current consumption during the test.
Preferably, each block further includes a plurality of bit line isolating gates. The bit line isolating gates are provided for the bit line pairs. Each bit line isolating gate is connected between the corresponding bit line pair and the corresponding sense amplifier. The semiconductor memory device further includes a turn-off circuit. The turn-off circuit causes the bit line isolating gates to turn off in response to the test signal.
When the plurality of bit line isolating gates are turned off in response to the test signal, the plurality of bit line pairs are disconnected from the corresponding sense amplifiers. As a result, it is unnecessary to charge/discharge the bit line pairs while repeating the data writing, so that the current consumption is reduced.
According to a still further aspect of the present invention, the semiconductor memory device includes a plurality of bit line pairs, a plurality of sense amplifiers, an input/output line pair, a plurality of column select gates, an equalizing circuit, a first turn-on circuit, and a second turn-on circuit. The sense amplifiers are provided for the bit line pairs. Each sense amplifier is connected to the corresponding bit line pair. The column select gates are provided for the bit line pairs. Each column select gate is connected between the corresponding bit line pair and the input/output line pair. The equalizing circuit is connected to the input/output line pair. The first turn-on circuit causes the column select gates to turn on in response to a test signal. The second turn-on circuit causes the equalizing circuit to turn on in response to the test signal.
In this semiconductor memory device, the plurality of column select gates and the equalizing circuit are turned on in response to the test signal, and the plurality of bit line pairs are connected to the input/output line pair, and further the input/output line pair is short-circuited. As a result, a leakage current flows between two sense nodes of the respective sense amplifiers via the corresponding column select gates, the input/output line pair and the equalizing circuit. Accordingly, large stress can be imposed on the column select gates.
According to yet another aspect of the present invention, the semiconductor memory device includes an input/output line pair, an equalizing circuit, and a plurality of blocks. The equalizing circuit is connected to the input/output line pair. Each block is selected in response to a corresponding block select signal. Each block includes a plurality of bit line pairs, a plurality of sense amplifiers, and a plurality of column select gates. The sense amplifiers are provided for the bit line pairs. Each sense amplifier is connected to the corresponding bit line pair. The column select gates are provided for the bit line pairs. Each column select gate is connected between the corresponding bit line pair and the input/output line pair. The semiconductor memory device further includes a first turn-on circuit and a second turn-on circuit. The first turn-on circuit causes the column select gates in selected one of the blocks to turn on in response to a test signal. The second turn-on circuit causes the equalizing circuit to: turn on in response to the test signal.
In this semiconductor memory device, the plurality of column select gates and the equalizing circuit are turned on in response to the test signal, and the plurality of bit line pairs are connected to the input/output line pair, and further the input/output line pair is short-circuited. As a result, a leakage current flows between two sense nodes of the respective sense amplifiers via the corresponding column select gates, the input/output line pair and the equalizing circuit, and large stress is imposed on the column select gates. In addition, the bit line pairs only within the selected block are connected to the input/output line pair, and the bit line pairs within a non-selected block are not connected thereto. Thus, the current consumption during the test is reduced.
According to the present invention, the transistor constituting the word line driver is forcibly turned on in response to a test signal, and thus, a through current flows in the word line driver even when the word line is not selected. As a result, it is possible to impose large stress on the transistor constituting the word line driver.
Further, a plurality of column select gates are forcibly turned on in response to a test signal, and thus, a plurality of sense amplifiers are connected to the input/output line pair. As a result, it is possible, by repeating writing of H-level data and L-level data, to impose large stress on the transistor constituting the column select gate.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.